Hola, estoy tratando de crear una ALU de 16 bits a partir de varias ALU de 1 bit. Creé un paquete llamado basic_alu1 que contiene un componente de la ALU de 1 bit. El código para esto es:

library ieee;
use ieee.std_logic_1164.all;
package basic_alu1 is
component alu1
    port (a, b: std_logic_vector(1 downto 0);
            m: in std_logic_vector(1 downto 0);
            result: out std_logic_vector(1 downto 0));
end component;
end package basic_alu1;


library ieee;
use ieee.std_logic_1164.all;
entity alu1 is
    port (a, b: std_logic_vector(1 downto 0);
    m: in std_logic_vector(1 downto 0);
    result: out std_logic_vector(1 downto 0));
end alu1; 
architecture arch1 of alu1 is 
begin
 process(a, b, m)
 begin
 case m is
 when "00" =>
    result <= a + b;
  when "01" =>
    result <= a + (not b) + 1;
  when "10" =>
    result <= a and b;
  when "11" =>
    result <= a or b;
end case
 end process
 end arch1

Entonces, para crear la ALU de 16 bits, estoy usando un bucle for generate e instanciar múltiples copias de alu1. Mi pregunta es cómo puedo poner el contador dentro y fuera del mostrador y cómo puedo tener una verificación de desbordamiento. Mi código principal es:

library ieee;
use ieee.std_logic_1164.all;
use work.basic_alu1.all;

entity alu16 is
  port (input_a : in std_logic_vector(15 downto 0);
        input_b : in std_logic_vector(15 downto 0);
        mode : in std_logic_vector(1 downto 0)
        result_x4 : out std_logic);
end alu16;

architecture structural of alu16 is
begin
G1 : for i in 0 to 15 generate
begin
    alu_16 : entity work.basic_alu1
    port map (
    a => input_a(i),
    b => input_b(i),
    m => mode,
    result => result_x4(i));
end generate;