Я должен написать код

Alu.v

module ALU(
    src1_i,
    src2_i,
    src3_i,
    src4_i,
    ctrl_i,
    result_o,
    zero_o
    );

//I/O ports
input  [32-1:0]  src1_i;
input  [32-1:0]  src2_i;
input  [4-1:0]   src3_i;//shmat is 5 bits instruction[10:6]
input  [15-1:0]  src4_i;//ori have to deal with 'zero-extended' number
input  [4-1:0]   ctrl_i;

output [32-1:0]  result_o;
output           zero_o;

//Internal signals
reg    [32-1:0]  result_o;
wire             zero_o;

//Parameter
assign zero_o = (result_o == 0);
//Main function
always @(*) begin
    case(ctrl_i)
        0 :result_o